This invention relates generally to creating precise exceptions, and more particularly, to creating precise exceptions by use of a mini-refresh.
Most microprocessor architectures define that exception conditions must trap to software at a precise point in execution, usually immediately following the instruction that created the exception condition. A typical type of execution is a floating point underflow or overflow when the results exceed the bounding ranges of numbers. An example of an architecture is the PowerPC architecture. The PowerPC architecture defines four different modes of execution for floating point exceptions: ignore exceptions mode; imprecise non-recoverable mode; imprecise recoverable mode; and precise mode. Many programs are executed in an imprecise mode that allows instructions to be executed out of order. On exceptions, execution is halted at or after the instruction causing the exception. If execution is halted after the instruction causing the exception, then all state data is updated for every instruction in serial order up to the point where execution is halted, even if the execution is out of order. This mode is optimized by hardware design. The precise mode is usually implemented by not pipelining any floating point instructions which may result in execution times on the order of five to seven times slower than imprecise mode. It would be desirable to be able to improve the performance of the microprocessor when utilizing the precise mode of operation.